Logical elements and computer units. Topic: logical elements and typical computer components. Logical elements and typical computer components

The physical components and circuits that make up the MP and MPS are their hardware. The equipment is capable of performing only a limited set of elementary operations. All others are functional. capabilities are achieved programmatically, that is, through the appropriate organization of a certain set and sequence of elementary machine operations.

Although in MP the hardware is subordinate to the software, both are at the complete disposal of the developer. Therefore, it is necessary to be well aware of what opportunities they provide.

The hardware of the MP and MPS is a set of repeatedly repeating standard logical nodes, which, in turn, represent circuits of standard logical elements.

Typical logic nodes include flip-flops, registers, counters, adders, decoders, multiplexers, bus systems, memories, etc.

From the point of view of information transformation methods, some of these nodes can be classified as combinational circuits, with the help of which arithmetic and logical operations are performed on two multi-bit words.

Combinational circuits are circuits without memory.

The other part is sequential circuits that carry out operations of storing, shifting, counting and transmitting information. Sequential circuits contain storage elements (SE).

The functionality of the MP is determined mainly by its combinational part, which forms the basis of the ALU.

Due to limitations on the volume of the manual, only buses will be considered below and the types of storage devices will be briefly described.

The principle of trunking provides the main way to reduce the number of connections in systems - the use of buses. The number of possible connections to a particular block is limited by the layout restrictions of integrated circuits or printed circuit boards. Moreover, it is generally desirable to minimize the number of connections, since they constitute the main part of the cost of the device.

Buses are common information channels, i.e. channels used by many devices in a system. In general, information on buses is transmitted in the form of words, which are a group of bits. Individual bits of a word can be transmitted over separate lines in the bus, or they can be transmitted over a single line sequentially in time. In the first case, the buses are called parallel, and in the second - serial.

Thus, a bus is a line or set of lines that interconnects individual logical devices and allows one device to send data to one or more other devices.

The bus can be unidirectional - in this case, some devices always act as senders, and others - always as receivers; the bus can be bidirectional - in this case, each device connected to the bus can at some point send signals to other devices.

From a technical point of view, the method of exchanging information via buses comes down to creating bidirectional buffer cascades with three stable states and implementing temporary multiplexing of exchange channels.

Examples of physical implementation of buses are: a special-design bus consisting of flexible wires, and a bus made in the form of a printed circuit. At any point in time, knowing the logical state of the bus, you can completely determine the path that data takes in the system from one point to another.

For microprocessor systems, the most common architecture is with three buses: address, data and control. The address bus is always unidirectional (relative to the MP).

When using a bus organization both inside a chip and when connecting several LSIs to one external bus, difficulties arise due to the methods of connecting several elements to one line of a common bus.

The ability to connect several inputs of logical elements to the bus is limited only by the load capacity of the circuits to the output of which this bus is connected. When using powerful buffer circuits, the load capacity is sufficient for most practical applications of a bus organization.

It is more difficult to organize the connection of the outputs of several elements to one bus. There are three known ways to solve this problem: logical union; combining using open collector circuits (“wiring logic”); fusion using tri-state circuits.

Feature Analysis in various ways the organization of common buses in MP and MPS allows us to draw conclusions that are confirmed by practical developments: when organizing internal MP buses, as a rule, logical combining and combining using open-collector circuits are used; When organizing highways external to the MP, as a rule, three-state logic is used.

An element is the smallest functional part into which a computer can be divided during logical design and technical implementation. According to their functional purpose, computer elements can be divided into: logical (implementing one of the functions of the algebra of logic); storage (flip-flops for storing single-digit binary numbers); auxiliary (for the formation and generation of pulses, timers, indicator elements, level converters, etc.).

A node is a collection of elements that implements one of the machine operations. There are two types of computer nodes: combinational; combinational nodes include adders, comparison circuits, encoders, decoders, multipliers, programmable logic matrices, etc. accumulating (with memory). triggers, registers, counters, etc. that accumulate nodes.

The encoder (encoder) converts a single signal at one of the inputs into an n-bit binary code. It finds its greatest application in information input devices (control panels) for converting decimal numbers into the binary number system. Inputs Outputs X Y 3 Y 2 Y 1 Y 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 Y 0=X 1+X 3+X 5+X 7+X 9 Y 1=X 2+X 3+X 6+X 7 Y 2=X 4+X 5+X 6+X 7 Y 3= X 8+X 9.

A decoder (decoder) is a node that converts the code arriving at its inputs, and the signal at only one of its outputs.

A multiplexer is a node designed to interrogate and transmit input information signals to one output circuit. Only one single-bit or multi-bit input circuit is selected at any time. UGO – conditional graphic display

A digital comparator is a combinational logical device designed to compare numbers represented in binary codes. The number of comparator inputs is determined by the bit depth of the codes being compared. Three signals are usually generated at the comparator output:

A binary adder is a logical operating unit that performs arithmetic addition of the codes of two numbers. There are two types of adder circuits: Half adder; Full adder.

Half adder - designed for adding single-digit numbers. binary numbers without taking into account carryover from the previous category. Let's make a table of logical values ​​for the adder, where A, B are terms, P and S are the carry and the place digit for the sum, respectively.

Computer elements and components.

A computer element is the smallest structural and functional part of a computer, which is used in its logical design and technological implementation. According to their purpose, they are divided into logical, storage and auxiliary.

Logical elements implement logical operations and are used both to build complex logical circuits (nodes) and to control the operation of individual computer blocks and devices.

Storage elements are designed to store and output binary information.

Auxiliary elements are most often used to provide energy and coordinate the operation of various computer blocks.

Let's consider the principle of construction and operation of elements and assemblies widely used in computers.

Trigger - an elementary digital automaton with two stable states. State 0 at output Q corresponds to the off state, and Q=1 to the on state. Triggers store information and remain in a given state after the switching signals cease. They are widely used in digital information processing.
According to the method of organizing logical connections that determine the features of functioning, triggers RS, T, D, JK are distinguished. Of these, the JK trigger is called universal, since all other types of triggers can be obtained from it.

The principle of operation of a JK flip-flop is well explained in the transition graph.

JK trigger switching circuits:

Asynchronous T trigger is a counting trigger, every two signals at the T input form one signal at the output.

Synchronous T trigger is a counting trigger, every two signals at the C input form one output signal if there is a logical 1 at the T input.

Synchronous D flip-flop - implements a time delay function. Operates according to the following transition table.

An asynchronous RS trigger is an elementary digital automaton with two stable states and two inputs R and S, operating in accordance with the following transition table.

Synchronous RS trigger differs from asynchronous RS triggers in that, in addition to information inputs, it has a synchronization input C. When C = 0, the trigger is in information storage mode. When C=1, a synchronous flip-flop works like an asynchronous RS flip-flop.

Registers - these are computer nodes that serve to store information in the form of machine words or parts thereof, as well as to perform certain logical transformations on words. They are digital Mili machines made on triggers.
Registers are capable of performing the following operations:
- setting the register to state 0 or 1 (on all outputs);
- receiving and storing n bit words in the register;
- shifting the binary code of a word stored in the register to the right or to the left by a specified value of bits;
- converting the code of a stored word into a sequential one, and vice versa, when receiving or issuing binary data;
- bitwise logical operations.

Below is a conventional graphic designation of the universal register and the purpose of its outputs:

Counters - computer nodes that count and store the code for the number of counted signals. They are digital Moore automata, in which the new state of the counter is determined by its previous state and the state of the logical variable at the input.
The internal state of the counters is characterized by a conversion factor K, which determines the number of its stable states. The main parameters are resolution (the minimum time between two signals that are reliably recorded) or maximum speed and information capacity. The designation and purpose of the reverse counter terminals is shown in the figure below.

Decoder, or electoral scheme, - This is a computer node in which each combination of input signals corresponds to the presence of a signal on one very specific output bus (combination device). Decoders are widely used to convert binary codes into control signals for various computer devices.

Encoder, or encoder, - This is a computer node that converts a unitary code into some positional code. If the output code is binary positional, then the encoder is called binary. With the help of encryptors, it is possible to convert the digits of decimal numbers into binary representation using any other BCD code.

Code converters - These are computer nodes designed to encode numbers. The number of code converters includes: binary-to-binary decimal converters, digital display converters, converters of direct code of binary numbers to reverse or complementary code, etc.

Multiplexers - These are nodes that convert parallel digital codes into serial ones. In this device, the output is connected to one of the inputs depending on the value of the addressable inputs. Multiplexers are widely used for the synthesis of combinational devices, as this helps to significantly reduce the number of chips used.

Demultiplexers - These are nodes that convert information from serial form to parallel form. Information input D is connected to one of the Qi outputs determined by the address signals A0 and A1.

Adder - This is the node in which the arithmetic operation of summing the digital codes of two binary numbers is performed.

Using single-bit adders, you can build multi-bit adders.

Individual task No. 4 (Lesson No. 1)

(To LR No. 2 “Study of operational units of the control center”)

Device diagrams are presented in the corresponding section of the laboratory work.

Task 1: Implement a mode for writing and storing a given code for a parallel memory register

Task 2: Implement a mode for writing and storing a given code for a sequential shift register. It is necessary to take into account that recording is carried out starting from the most significant digit.

Options for source data for analyzing register operation Table 1

Task 3: Implement preset and counting modes for counters for given initial data:

Options for initial data for analyzing the operation of reversible meters Table 3

Task 4: Perform an analysis of the operation of a parallel adder with serial carry for the source data:

Options for initial data for analyzing the operation of the adder Table 3

Topic 3. Typical DH elements and assemblies

Individual task No. 5 (Lesson No. 2)

(To LR No. 3 “Research of code conversion nodes,

Signal switching and control center")

Task 1. For a 2-input decoder (converter of a binary two-digit code X 2 X 1 into a seven-segment indicator code), compose and minimize a logical equation for one of the segments. Draw a diagram of the implementation of this equation using the elements OR – NOT, AND – NOT. To do this, use the truth table of the decoder (Table 1).

Table 1

Task 2: Based on the LF, analyze the operation (fill in the truth table) of the digital single-digit comparator of circuit No. 2 (PZ No. 4). On LR No. 3, assemble circuit No. 2, check the resulting truth table

Task 3: For the LF, conduct an analysis of the work (fill in the truth table) of the majoritation scheme (PZ No. 4). On LR No. 3, assemble the circuit, check the resulting truth table

Task 4: According to the LF, analyze the operation (fill in the truth table) of the parity (odd parity) control circuit of units of parallel two-bit code (PZ No. 4). On LR No. 3, assemble the circuit, check the resulting truth table

Task 5: According to the LF, analyze the operation (fill in the truth table) of the parity coding scheme of a parallel two-bit code (PZ No. 4). On LR No. 3, assemble the circuit, check the resulting truth table

Task 6: According to the LF, analyze the operation (fill in the truth table) of the parity control circuit of a parallel two-bit code (PZ No. 4). On LR No. 3, assemble the circuit, check the resulting truth table

Task 7: Based on the LF, analyze the operation (fill in the truth table) of the transmission circuit of a parallel two-bit code with parity check (PZ No. 4). On LR No. 3, assemble the circuit, check the resulting truth table

Topic 4. Microprocessor technology

Individual task No. 6 (PZ No. 3)

(To LR No. 4 “Study of microprocessor operation”)

Task No. 1. Using the command system of the KR580IK80A microprocessor, determine the operation codes for the commands:

Task No. 2. Using the MP KR580IK80A command system, compose a program in machine code. The computational problem and initial data are presented in the table.

Based on the result of an arithmetic operation individual task No. 3 determine the state (describe by digits-attributes in the binary number system) of the attribute register F .

Assignment for LR No. 4 Study of the operation of the microprocessor: Each student must complete an individual task on programming microprocessors.